For conventional active matrix liquid crystal display apparatuses provided with external driver ICs, in order to meet a demand for higher precision, it is necessary to increase a number of connection terminals and to provide these connection terminals at narrower pitches. The foregoing conventional active matrix liquid crystal display apparatuses therefore have a problem in that the mounting process becomes complicated. In response, the time division driving method has been proposed. In the time division driving method, a plurality of signal lines are divided into blocks, and signals to be applied to the signal lines in each block are outputted from a driving circuit in time series, and time division switches are provided for the signal lines in each block, which divide the signals outputted from the driver IC in time series into time segments to be sequentially applied to the signal lines. With this time division driving method, it is possible to reduce the number of connection terminals.
A typical depiction of the structure of an active matrix liquid crystal display apparatus adopting the time division driving method is shown in FIG. 11. On the active matrix substrate 101, formed are a plurality of scanning signal lines and a plurality of data signal lines in a form of a matrix, and a plurality of pixels provided at respective interactions between the data signal lines and the scanning signal lines to form a liquid crystal display panel. These pixels are divided, into blocks, each block corresponding to a combination of video signals for R, G and B to be supplied to respective pixels by time division. Namely, a pixel PR (n, m) for R, a pixel PG (n, m) for G and a pixel PB(n, m) for B which are successively aligned in a direction of a scanning signal line constitute a pixel block. Each pixel has a pixel capacitance CL and a switching element SW.
The respective ends on one side of the scanning signal lines GL1, GL2, . . . and GLn are connected to the output terminals in the corresponding lines of the scanning signal line driving circuit (not shown). The scanning signal line driving circuit carries out a scanning operation in a vertical direction by selecting pixels line by line by sequentially supplying scanning pulses to the scanning signal lines GL1, GL2, . . . . GLn. Further, a plurality of driver ICs (not shown) are provided for supplying a predetermined voltage according to the image data to data signal lines SL1R, SL1G, SL1B, . . . , SLmR, SLmG, SLmB, . . . as an external circuit of the liquid crystal display panel.
To realize the time division driving, a plurality of signal lines are divided into signal line groups, and each driver IC is arranged so as to output signals to be applied to a plurality of signal lines in the signal line group in time series. To realize the foregoing structure, between the output signal lines SL1, SL2, SL3, . . . , SLm of the driver IC and the data signal lines SL1R, SL1G, SL1B, . . . SLmR, SLmG, SLmB, . . . provided are analog switches (time division switches) of the CMOS, NMOS or PMOS structure.
FIG. 12 shows the connection state of the time division switches when adopting the time division driving method in which a transmission time is divided into three time segments correspondingly to R, G and B. In this time division driving method, from respective output terminals of the driver ICs, signal voltages for three pixels for R, G and B are outputted sequentially in time series via the output signal lines SL1, SL2, SL3, . . . SLm. Specifically, as shown in the timing chart of FIG. 13, as output signals from the driver IC, video signals for DATAmR, DATAmG and DATAmB for respective pixels R, G and B are outputted to the output signal line SLm. As shown in FIGS. 11 and 12, between the output signal line SLm and three data signal lines SLmR, SLmG and SLmB, provided are time division switches ASWmR, ASWmG and ASWmB. The time division switches are provided in the number of three for each output signal line (here, one signal line on the side of the driver IC connected to SLmR, SLmG and SLmB is called the output signal line SLm) corresponding to the number of time segments (three) in the time division method.
The concrete structure of a set of time division switches ASWmR, ASWmG and ASWmB will be explained in reference to the circuit diagram of FIG. 12.
The respective input terminals of these three time division switches ASWmR, ASWmG and ASWmB are connected in common to the output signal line SLm. As a result, the signal potentials outputted in time series from the driver IC are applied to respective input terminals of these three time division switches ASWmR, ASWmG and ASWmB via the output signal line SLm. On the other hand, output terminals of these time division switches ASWmR, ASWmG and ASWmB are connected to respective ends on one side of the data signal lines SLmR, SLmG, SLmB.
The three control signal lines Rct1, Gct1, Bct1 are provided for each time division switch along the scanning signal lines GL1, GL2, . . . and GLn, wherein a control input terminal of the time division switch ASWmR is connected to the control line Rct1, the control input terminal of the time division switch ASWmG is connected to the control line Gct1, and the control input terminal of the time-division switch ASWmB is connected to the control line Bct1.
To these three control signal lines Rct1, Gct1, and Bct1, supplied are control signals Rct1, Gct1, and Bct1 (for convenience in explanations, same reference symbols are used as the control signals) for selecting three time division switches in each group. These three control signal lines Rct1, Gct1, and Bct1 are signals for sequentially setting ON the three time division switches in each group in sync with signal potentials in time series outputted from the driver IC.
These time division switches ASWmR, ASWmG and ASWmB are sequentially set ON by receiving scanning signal line selection signals GL1, GL2 and GL3, . . . GLn (for convenience in explanations, same reference symbols are used as the scanning signal lines) as supplied externally, and the signals as outputted in time series to the output signal lines SL1, SL2, SL3, SLm, . . . from the driver IC are supplied to the corresponding signal line by time division in which one horizontal scanning period is divided into three time segments.
Japanese Unexamined Patent Publication No. 338438/1999 (Tokukaihei 11-338438, published on Dec. 10, 1999), Japanese Unexamined Patent Publication No. 234237/1996 (Tokukaihei 8-234237, published on Sep. 13, 1996), Japanese Unexamined Patent Publication No. 138851/1994 (Tokukaihei 6-138851, published on May 20, 1994), and Japanese Unexamined Patent Publication No. 322216/1992 (Tokukaihei 4-322216, published on Nov. 12, 1992) disclose the generally used SSD (Source Shared Driving Method).
In FIG. 12, when signal potentials are inputted to the data signal lines SLmR, SLmG, SLmB from the driver IC, the data signal line, corresponding to the time division switch ASWmR in the OFF state, becomes in the high impedance state, and the data signal line is therefore liable to be affected by externally supplied potentials, for example, and the potential of the signal line is therefore liable to be fluctuated. As illustrated in FIG. 12, for example, the data signal line SLmR includes the capacitive coupling component between other data signal lines SLmG and SLm-lB. As shown in the timing chart of FIG. 13, when the time-division switch ASWmR is switched OFF at time Tre when the video signal DATAmR is supplied, the data signal line SLmR is set in the floating state, and when the time division switch ASWmG is set in the ON state at time Tgs, the data signal line SLmR is subjected to fluctuations in potential as being affected by the fluctuations in potential of the data signal line SLmG. Similarly, when the time-division switch ASWmG is switched OFF at time Tge when the video signal DATAmG is supplied, the data signal line SLmG is set in the floating state, and when the time division switch ASWmB is set in the ON state at time Tbs, the data signal line SLmG is subjected to fluctuations in potential as being affected by the fluctuations in potential of the data signal line SLmB.
As described, when the video signals are supplied to the data signal line by time division, only the data signal line SLmB charged by the video signal DATAmB last is not affected by the fluctuations in potential by the capacitive coupling, and upon completing the function of the scanning signal GLn which controls the charge in a pixel, a display corresponding to the potential at that time is made in the display section. Here, fluctuations in potential ΔV due to the capacitive coupling are accumulated in the order of the switching signals Ron→Gon→Bon, which results in that the respective potentials VSLmR, VSLmG and VSLmB of the data signal lines SLmR, SLmG and SLmB become VSLmR>VSLmG>VSLmB when a display is made in gray color of the intermediate tone by setting the potentials of the video signals DATAmR, DATAmG and DATAmB to be equal. Therefore, when the normally white mode is selected for the liquid crystal display mode, a display becomes in dark blue gray.